1. Technical Field
This disclosure relates to semiconductor memories and more particularly, to an improved method and apparatus for replacing defective row/column lines.
2. Description of the Related Art
CMOS technology has evolved such that the computer market has rapidly opened to a wide range of consumers. Today, multi-media requires at least 32 Mb of DRAM and preferably 64 Mb. This increases the relative cost of the memory system within the computer. In the near future, it is likely that 128 Mb and 512 Mb computers will become commonplace, which suggests a potential demand for 256 Mb and 1 Gb DRAMS (Dynamic Random Access Memory) and beyond. Despite the huge array size and lithographic difficulties that ensue, it is more important than ever to increase the chip yield. Process engineers are constantly attempting to reduce, and ultimately eliminate, or at the very least, mask defects. Faults that inevitably remain in the chip are generally overcome using special circuit designs and more specifically, redundancy replacement.
A typical redundancy architecture, which is commonly used for low density DRAMs is shown in FIG. 1a. FIG. 1a depicts a plurality of spare elements (redundancy cells) used for replacing defective elements (defective cells) within the domain, and which are appended to each block (sub array) comprising a plurality of elements (cells). The sense amplifiers (not shown) are located between adjacent blocks, providing support not only for elements but also the redundancy elements. Each redundancy unit (RU) is comprised of few redundancy elements (REs), (e.g., two RE per RU are illustrated therein), and which are used to repair existing faults (labeled X) within the corresponding block. This scheme, labeled intra-block replacement, increases the redundancy area overhead as the number of blocks increases for high-density memories, since each block composes a domain for the replacement, and the domains in different blocks are mutually exclusive to each other. This requires at least one or preferably two RUs in each block. Thus, the efficiency of the RUs is rather poor in view of its inflexibility which reduces the chip yield substantially when faults are clustered in a given block. The above-mentioned concept is embodied in a configuration described in the article by T. Kirihata et al., entitled "A 14 ns 4 Mb DRAM with 300 mW WActive Power", published in the IEEE journal of Solid State Circuits, Vol. 27, pp. 1222-1228, September 1992.
Another redundancy architecture, known as a flexible redundancy replacement configuration, is shown in FIG. 1b, wherein a memory is depicted having a redundancy block (array) as a large domain of RUs to selectively replace failing elements anywhere in the memory. In this configuration, REs within the RU can repair faults (labeled X) located in any block within the memory. The advantage of this arrangement over the previously described intra-block replacement is that one section, namely a redundancy block, having a certain number of RUs may advantageously be used to service any number of blocks forming the memory. This translates into a substantial savings of real estate for the RUs over the previous scheme. It does, however, require additional sense amplifiers to support the redundancy block. More details regarding the above configurations and the various trade-off may be found in an article by T. Kirihata et al., "A fault-Tolerant Design for 256 Mb DRAMs" published in the Digest of Technical Papers of the 1995 Symposium on VLSI Circuits, pp. 1525-1534, October 1997; in and article by T. Sugibayashi et al., "A 30 ns 256 Mb DRAM with Multi-divided Arrays Structure", published in the IEEE Journal of Solid State Circuits, Vol. 28, pp. 1092-1098, November 1993; and in an article by H. L. Kalter et al., "A 50 ns 16 Mb DRAM with a 10 ns Data Rate and On-Chip ECC", published in the IEEE Journal of Solid State Circuits, Vol. 25, pp. 1118-1128, October 1990.
Another redundancy Architecture, shown in FIG. 1c, employs a flexible redundancy replacement with an intra-block redundancy configuration. In this architecture, RUs are integrated in each sub-array, as in the intra-block replacement. It does, however, allow the use of RUs to repair a fault flexibly for other blocks, as in the flexible redundancy replacement with redundancy block. Note that the additional sense amplifiers are not required for enabling the flexibility, resulting in less design space overhead. However, the data contention problem occurs when two or more sub-arrays, which have a same flexible domain for the replacement, are activated simultaneously. The detailed data contention problem is described with respect to FIG. 2. FIG. 2 shows a 16 Mb bank 12, consisting of four 4 Mb blocks 16. Each block contains a plurality of wordlines (WL), each contacting a plurality of cells. Each block 16 also contains a plurality of redundancy wordlines (RWLs) 18, each containing a plurality of redundancy cells. For simplicity, the column redundancy are ignored, however, redundancy columns can also be integrated in a similar manner. Sense amplifiers 14 are typically arranged and shared between adjacent blocks 16. It is assumed that two wordlines (WL1 in block 1, and WL3 in block 3) are activated simultaneously. (Note that two WLs in block 0 and 1, or in blocks 2 and 3 cannot be activated simultaneously, since the sense amplifiers are shared between blocks 0 and 1 and blocks 2 and 3). The cell data from WL1 is amplified with sense amplifiers 14-b and 14-c, and the cell data from WL3 are amplified with sense amplifiers 14-d and 14-e. When the WL1 is defective, it should be replaced with redundancy wordline (RWL) as a redundancy replacement. A data contention problem occurs when the defective WL1 is replaced with RWL physically located in block 3. In this case, two wordline WL3 and RWL within block 3 are activated simultaneously. FIG. 3 is a detailed schematic, showing the WL3, RWL and sense amplifiers 24. The cells coupled to the WL3 and the redundancy cells couple to RWL store data independently. This makes sensing impossible, since two bit data is transferred to the pair of BLs for sensing. This problem is unavoidable when using the flexibly redundancy replacement with intra-block redundancy configuration. In conclusion, the FIG. 1c approach is only appreciable when one block is activated, otherwise, there is always a probability of data contention due to flexible redundancy replacement.
FIG. 4 shows the flexible redundancy replacement with redundancy block concept which is similar to the FIG. 1b. It is assumed that WL1 in block 0 and WL2 in block 2 are activated simultaneously. When WL2 is defective, it is replaced with RWL physically located in redundancy block. The data contention problem can be avoided, since the redundancy block as sense amplifiers 14R, although this could result in an area penalty. It is, however, still a data contention problem when the WL0 and WL2 are both defective, and replaced simultaneously with two RWLs physically located in a single redundancy block. Having two redundancy blocks can overcome the data contention, however, it requires additional sense amplifiers. In conclusion, the FIG. 1b approach is not suitable when multi-blocks are activated simultaneously.
The present invention overcomes this data contention problem in the multi-block activations, while allowing for flexible redundancy replacement spurting a plurality of blocks without having any additional sense amplifiers.